Cryptology ePrint Archive: Report 2021/1120

Simpira Gets Simpler: Optimized Simpira on Microcontrollers

Minjoo Sim and Siwoo Eum and Hyeokdong Kwon and Kyungbae Jang and Hyunjun Kim and Hyunji Kim and Gyeongju Song and Wai-Kong Lee and Hwajeong Seo

Abstract: Simpira Permutation is a Permutation design using the AES algorithm. The AES algorithm is the most widely used in the world, and Intel has developed a hardware accelerated AES instruction set (AES-NI) to improve the performance of encryption. By using AES-NI, Simpira can be improved further. However, low-end processors that do not support AES-NI require efficient implementation of Simpira optimization. In this paper, we introduce a optimized implementation of a Simpira Permutation in 8-bit AVR microcontrollers and 32-bit RISC-V processors, that do not support the AES instruction set. We firstly pre-computed round keys and omitted the Addroundkey. Afterward, the MixColumn and InvMixColumn of the final round (i.e. 12-th), which were added unnecessarily due to characteristics of Simpira using AES-NI, were omitted. In the AVR microcontroller, the Addroundkey consists of 16 operations, but it has been optimized by eliminating operations where the value of roundkeys is \texttt{0x00}, omitting Addroundkey to 4 operations. In the RISC-V processor, it is implemented using a same optimization technique of AVR implementation. We have carried out experiments 8-bit ATmega128 microcontroller and 32-bit RISC-V processor, which shows up-to \texttt{5.76$\times$ and 37.01$\times$} better performance enhancement than reference codes for the Simpira Permutation, respectively.

Category / Keywords: implementation / AES, Software Implementation, Simpira Permutation, 8-bit AVR Microcontroller, 32-bit RISC-V Processor

Date: received 2 Sep 2021

Contact author: minjoos9797 at gmail com, shuraatum at gmail com, hwajeong84 at gmail com, waikong lee at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20210903:065802 (All versions of this report)

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