Cryptology ePrint Archive: Report 2021/1117

All the Polynomial Multiplication You Need on RISC-V

Hwajeong Seo and Hyeokdong Kwon and Siwoo Eum and Kyungbae Jang and Hyunjun Kim and Hyunji Kim and Minjoo Sim and Gyeongju Song and Wai-Kong Lee

Abstract: Polynomial multiplication is a core operation for public key cryptography, such as pre-quantum cryptography (e.g. elliptic curve cryptography) and post-quantum cryptography (e.g. code-based cryptography and multivariate-based cryptography). For this reason, the efficient and secure implementation of polynomial multiplication has been actively conducted for high availability and security level in application services. In this paper, we present all polynomial multiplication methods on modern 32-bit RISC-V processors. We re-designed expensive implementations of polynomial multiplication on legacy microcontrollers (e.g. 8-bit AVR, 16-bit MSP, and 32-bit ARM) for new instruction sets of 32-bit RISC-V processors. Secondly, we suggest the optimal operand length for each polynomial multiplication on 32-bit RISC-V processors. With this implementation technique and Karatsuba algorithm, we achieved scalable features, which ensures the polynomial multiplication in any operand lengths with reasonably fast performance. Third, we propose instruction set extensions for the optimal implementation of polynomial multiplication on 32-bit RISC-V processors. This new feature introduces significant performance enhancements. Lastly, the proposed implementation is a public domain and following researchers can easily re-produce the result.

Category / Keywords: implementation / Secure Polynomial Multiplication, Side Channel Attack, Cache Attack, Constant Timing, RISC-V Processors, Instruction Set Extensions

Date: received 2 Sep 2021

Contact author: hwajeong84 at gmail com, waikong lee at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20210903:065707 (All versions of this report)

Short URL: ia.cr/2021/1117


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