Cryptology ePrint Archive: Report 2021/1053

XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage

Thinh H. Pham and Ben Marshall and Alexander Fell and Siew-Kei Lam and Daniel Page

Abstract: Side-channel analysis (SCA) attacks pose a major threat to embedded systems due to their ease of accessibility. Realising SCA resilient cryptographic algorithms on embedded systems under tight intrinsic constraints, such as low area cost, limited computational ability, etc., is extremely challenging and often not possible. We propose a seamless and effective approach to realise a generic countermeasure against SCA attacks. XDIVINSA, an extended diversifying instruction agent, is introduced to realise the countermeasure at the microarchitecture level based on the combining concept of diversified instruction set extension (ISE) and hardware diversification. XDIVINSA is developed as a lightweight co-processor that is tightly coupled with a RISC-V processor. The proposed method can be applied to various algorithms without the need for software developers to undertake substantial design efforts hardening their implementations against SCA. XDIVINSA has been implemented on the SASEBO G-III board which hosts a Kintex-7 XC7K160T FPGA device for SCA mitigation evaluation. Experimental results based on non-specific t-statistic tests show that our solution can achieve leakage mitigation on the power side channel of different cryptographic kernels, i.e., Speck, ChaCha20, AES, and RSA with an acceptable performance overhead compared to existing countermeasures.

Category / Keywords: implementation / Side-Channel Attacks, Hiding countermeasures, Hardware Diversification, Instruction Set Extension, RISC-V

Date: received 13 Aug 2021

Contact author: th pham at bristol ac uk

Available format(s): PDF | BibTeX Citation

Version: 20210816:131550 (All versions of this report)

Short URL: ia.cr/2021/1053


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