Cryptology ePrint Archive: Report 2021/1010

Circuit friendly, post-quantum dynamic accumulators from RingSIS with logarithmic prover time

Endre (Silur) Abraham

Abstract: Mainstream hash functions such as SHA or BLAKE while generally efficient in their implementations, are not suitable for zero-knowledge boolean or arithmetic circuits due to their reliance on CPU designs. As a candidate hash function that uses only on trivial arithmetics which can be generalized to zeroknowledge circuits, the Ajtai lattice SIS-hasher has been proposed. In this paper we review Micciancio’s R-SIS generalization and argue about it’s circuit complexity, then we show how this R-SIS hasher can be used as a universal dynamic hash accumulator that has constant-time update and revocation complexity, and can be run on 16-bit hardware as well as smart contracts.

Category / Keywords: applications / rsis lattice accumulator zk circuit quantum

Date: received 29 Jul 2021

Contact author: silur at cryptall co

Available format(s): PDF | BibTeX Citation

Version: 20210806:072137 (All versions of this report)

Short URL: ia.cr/2021/1010


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