Paper 2021/004
LLMonPro: Low-Latency Montgomery Modular Multiplication Suitable for Verifiable Delay Functions
Ismail San
Abstract
This study presents a method to perform low-latency modular multiplication operation based on both Montgomery and Ozturk methods. The design space exploration of the proposed method on a latest FPGA device is also given. Through series of experiments on the FPGA using an high-level synthesis tool, optimal parameter selection of the proposed method for the low-latency constraint is also presented for the proposed technique.
Note: Table is fitted into the page.
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Preprint. MINOR revision.
- Keywords
- Montgomery modular multiplicationlow-latency implementationhigh-level synthesisFPGA.
- Contact author(s)
- isan83 @ gmail com
- History
- 2021-02-16: revised
- 2021-01-02: received
- See all versions
- Short URL
- https://ia.cr/2021/004
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2021/004,
author = {Ismail San},
title = {{LLMonPro}: Low-Latency Montgomery Modular Multiplication Suitable for Verifiable Delay Functions},
howpublished = {Cryptology {ePrint} Archive, Paper 2021/004},
year = {2021},
url = {https://eprint.iacr.org/2021/004}
}
