Cryptology ePrint Archive: Report 2021/004

LLMonPro: Low-Latency Montgomery Modular Multiplication Suitable for Verifiable Delay Functions

Ismail San

Abstract: This study presents a method to perform low-latency modular multiplication operation based on both Montgomery and Ozturk methods. The design space exploration of the proposed method on a latest FPGA device is also given. Through series of experiments on the FPGA using an high-level synthesis tool, optimal parameter selection of the proposed method for the low-latency constraint is also presented for the proposed technique.

Category / Keywords: implementation / Montgomery modular multiplication, low-latency implementation, high-level synthesis, FPGA.

Date: received 31 Dec 2020

Contact author: isan83 at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20210102:114042 (All versions of this report)

Short URL: ia.cr/2021/004


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