Cryptology ePrint Archive: Report 2020/930

The design of scalar AES Instruction Set Extensions for RISC-V

Ben Marshall and G. Richard Newell and Dan Page and Markku-Juhani O. Saarinen and Claire Wolf

Abstract: Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardised ISE. We survey the state-of-the-art industrial and academic ISEs for AES, implement and evaluate five different ISEs, one of which is novel. We recommend separate ISEs for 32 and 64-bit base architectures, with measured performance improvements for an AES-128 block encryption of 4 and 10 with a hardware cost of 1.1K and 8.2K gates respectivley, when compared to a software-only implementation based on use of T-tables. We also explore how the proposed standard bit-manipulation extension to RISC-V can be harnessed for efficient implementation of AES-GCM. Our work supports the ongoing RISC-V cryptography extension standardisation process.

Category / Keywords: implementation / AES, RISC-V, ISE

Date: received 27 Jul 2020, last revised 2 Oct 2020

Contact author: ben marshall at bristol ac uk

Available format(s): PDF | BibTeX Citation

Version: 20201002:111719 (All versions of this report)

Short URL: ia.cr/2020/930


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