Efficient and Fast Hardware Architectures for SIKE Round 2 on FPGA

Rami Elkhatib; Reza Azarderakhsh; Mehran Mozaffari-Kermani

Paper 2020/611

Efficient and Fast Hardware Architectures for SIKE Round 2 on FPGA

Rami Elkhatib, Reza Azarderakhsh, and Mehran Mozaffari-Kermani

Abstract

New primes were proposed for Supersingular Isogeny Key Encapsulation (SIKE) in NIST standardization process of Round 2 after further cryptanalysis research showed that the security levels of the initial primes chosen were over-estimated. In this paper, we develop a highly optimized $F_{p}$ Montgomery multiplication algorithm and architecture that further utilizes the special form of SIKE prime compared to previous implementations available in the literature. We then implement SIKE for all Round 2 NIST security levels (SIKEp434 for NIST security level 1, SIKEp503 for NIST security level 2, SIKEp610 for NIST security level 3, and SIKEp751 for NIST security level 5) on Xilinx Virtex 7 using the proposed multiplier. Our best implementation (NIST security level 1) runs 29\% faster and occupies 30\% less hardware resources in comparison to the leading counterpart available in the literature and implementations for other security levels achieved similar improvement.

Metadata

Available format(s): PDF
Category: Public-key cryptography
Publication info: Published elsewhere. https://ieeexplore.ieee.org/
Keywords: hardware architectures isogeny-based cryptography Montgomery multiplication post-quantum cryptography SIKE
Contact author(s): relkhatib2015 @ fau edu
razarderakhsh @ fau edu
History: 2020-05-25: received
Short URL: https://ia.cr/2020/611
License: CC BY

BibTeX

@misc{cryptoeprint:2020/611,
      author = {Rami Elkhatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani},
      title = {Efficient and Fast Hardware Architectures for {SIKE} Round 2 on {FPGA}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2020/611},
      year = {2020},
      url = {https://eprint.iacr.org/2020/611}
}