BSPL: Balanced Static Power Logic

Bijan Fadaeinia; Thorben Moos; Amir Moradi

Paper 2020/558

BSPL: Balanced Static Power Logic

Bijan Fadaeinia, Thorben Moos, and Amir Moradi

Abstract

The down-scaling of circuit technology has led to stronger leakage currents in CMOS standard cells. This source of power consumption is data dependent and can be utilized to extract secrets from cryptographic devices. We propose Balanced Static Power Logic (BSPL), the first leakage-balancing approach that achieves optimal data-independence with respect to drain-source leakage. We re-design fundamental standard cells in such a way that their leakage current is essentially constant, irrespective of inputs and outputs, barring process variations. Even in presence of considerable intra-die variations, modeled by Monte Carlo simulations, BSPL gates still maintain a significantly reduced mutual information between the circuit’s input and conducted leakage current.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Preprint. MINOR revision.
Contact author(s): thorben moos @ rub de
History: 2020-05-15: received
Short URL: https://ia.cr/2020/558
License: CC BY

BibTeX

@misc{cryptoeprint:2020/558,
      author = {Bijan Fadaeinia and Thorben Moos and Amir Moradi},
      title = {{BSPL}: Balanced Static Power Logic},
      howpublished = {Cryptology {ePrint} Archive, Paper 2020/558},
      year = {2020},
      url = {https://eprint.iacr.org/2020/558}
}