Cryptology ePrint Archive: Report 2020/558

BSPL: Balanced Static Power Logic

Bijan Fadaeinia and Thorben Moos and Amir Moradi

Abstract: The down-scaling of circuit technology has led to stronger leakage currents in CMOS standard cells. This source of power consumption is data dependent and can be utilized to extract secrets from cryptographic devices. We propose Balanced Static Power Logic (BSPL), the first leakage-balancing approach that achieves optimal data-independence with respect to drain-source leakage. We re-design fundamental standard cells in such a way that their leakage current is essentially constant, irrespective of inputs and outputs, barring process variations. Even in presence of considerable intra-die variations, modeled by Monte Carlo simulations, BSPL gates still maintain a significantly reduced mutual information between the circuit’s input and conducted leakage current.

Category / Keywords: implementation /

Date: received 13 May 2020

Contact author: thorben moos at rub de

Available format(s): PDF | BibTeX Citation

Version: 20200515:095558 (All versions of this report)

Short URL: ia.cr/2020/558


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