Cryptology ePrint Archive: Report 2020/465

Domain-Oriented Masked Instruction Set Architecture for RISC-V

Pantea Kiaei and Patrick Schaumont

Abstract: An important selling point for the RISC-V instruction set is the separation between ISA and the implementation of the ISA, leading to flexibility in the design. We argue that for secure implementations, this flexibility is often a vulnerability. With a hardware attacker, the side-effects of instruction execution cannot be ignored. As a result, a strict separation between the ISA interface and implementation is undesirable. We suggest that secure ISA may require additional implementation constraints. As an example, we describe an instruction-set for the development of power side-channel resistant software.

Category / Keywords: implementation / RISC-V, ISA, embedded systems security, SCA and countermeasures, domain-oriented masking

Original Publication (in the same form): The First International Workshop on Secure RISC-V (SECRISC-V) Architecture Design Exploration 2020

Date: received 21 Apr 2020, last revised 24 Apr 2020

Contact author: pantea95 at vt edu,pschaumont@wpi edu

Available format(s): PDF | BibTeX Citation

Version: 20200424:140114 (All versions of this report)

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