Cryptology ePrint Archive: Report 2020/185

Hardware Private Circuits: From Trivial Composition to Full Verification

Gaëtan Cassiers and Benjamin Grégoire and Itamar Levi and François-Xavier Standaert

Abstract: The design of glitch-resistant higher-order masking schemes is an important challenge in cryptographic engineering. A recent work by Moos et al. (CHES 2019) showed that most published schemes (and all efficient ones) exhibit local or composability flaws at high security orders, leaving a critical gap in the literature on hardware masking. In this paper, we first extend the simulatability framework of Belaïd et al. (EUROCRYPT 2016) and prove that a compositional strategy that is correct without glitches remains valid with glitches. We then use this extended framework to prove the first masked gadgets that enable trivial composition with glitches at arbitrary orders. We show that the resulting "Hardware Private Circuits'' approach the implementation efficiency of previous (flawed) schemes. We finally investigate how trivial composition can serve as a basis for a tool that allows verifying full masked hardware implementations (e.g., of complete block ciphers) at any security order. The tool checks that a synthesized HDL code fulfills the topological requirements of the composability theorems. As side products, we improve the randomness complexity of the best published refreshing gadgets, show that some S-box representations allow latency reductions and confirm practical claims based on implementation~results.

Category / Keywords: implementation / side-channel masking

Date: received 14 Feb 2020

Contact author: gaetan cassiers at uclouvain be

Available format(s): PDF | BibTeX Citation

Version: 20200218:090407 (All versions of this report)

Short URL: ia.cr/2020/185


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