Cryptology ePrint Archive: Report 2020/1259

Silent Two-party Computation Assisted by Semi-trusted Hardware

Yibiao Lu and Bingsheng Zhang and Weiran Liu and Lei Zhang and Kui Ren

Abstract: With the advancement of the trusted execution environment (TEE) technologies, hardware-supported secure computing becomes increasingly popular due to its efficiency. During the protocol execution, typically, the players need to contact a third-party server for remote attestation, ensuring the validity of the involved trusted hardware component, such as Intel SGX, as well as the integrity of the computation result. When the hardware manufacturer is not fully trusted, sensitive information may be leaked to the third-party server through backdoors, side-channels, steganography, and kleptography, etc. In this work, we introduce a new security notion called semi-trusted hardware model, where the adversary is allowed to passively and/or maliciously corrupt the hardware component. Therefore, she can learn the input of the hardware component and might also tamper the output. We show that two-party computation (2PC) can still be significantly sped up in this new model. When the semi-trusted hardware is instantiated by Intel SGX, to generate 10k random OT's, our protocol is 24X and 450X faster than the EMP-IKNP-ROT in the LAN and WAN setting, respectively. For the AES-128, SHA-256, and SHA-512 evaluation, our protocol is 4.9-5.4X and 40-46X faster than the EMP-SH2PC in the LAN and WAN setting, respectively. We also show how to achieve malicious security with little overhead.

Category / Keywords: cryptographic protocols / 2PC,semi-trusted hardware model,garbled circuit

Date: received 11 Oct 2020, last revised 17 Jan 2021

Contact author: luyibiao at zju edu cn,bingsheng@zju edu cn

Available format(s): PDF | BibTeX Citation

Version: 20210118:065236 (All versions of this report)

Short URL:

[ Cryptology ePrint archive ]