Cryptology ePrint Archive: Report 2020/117

Efficient BIKE Hardware Design with Constant-Time Decoder

Andrew Reinders and Rafael Misoczki and Santosh Ghosh and Manoj Sastry

Abstract: BIKE (Bit-flipping Key Encapsulation) is a promising candidate running in the NIST Post-Quantum Cryptography Standardization process. It is a code-based cryptosystem that enjoys a simple definition, well-understood underlying security, and interesting performance. The most critical step in this cryptosystem consists of correcting errors in a QC-MDPC linear code. The BIKE team proposed variants of the Bit-Flipping Decoder for this step for Round 1 and 2 of the standardization process. In this paper, we propose an alternative decoder which is more friendly to hardware implementations, leading to a latency-area performance comparable to the literature while introducing power side channel resilience. We also show that our design can accelerate all key generation, encapsulation and decapsulation operations using very few common logic building blocks.

Category / Keywords: public-key cryptography / Post-Quantum Cryptography, PQC, BIKE, QC-MDPC, Bit-flipping Decoder, Hardware Acceleration, NIST PQC Standardization Project

Date: received 4 Feb 2020

Contact author: andrew h reinders at intel com, rafael misoczki@intel com, santosh ghosh@intel com, manoj r sastry@intel com

Available format(s): PDF | BibTeX Citation

Version: 20200206:144417 (All versions of this report)

Short URL: ia.cr/2020/117


[ Cryptology ePrint archive ]