Paper 2020/117
Efficient BIKE Hardware Design with Constant-Time Decoder
Andrew Reinders, Rafael Misoczki, Santosh Ghosh, and Manoj Sastry
Abstract
BIKE (Bit-flipping Key Encapsulation) is a promising candidate running in the NIST Post-Quantum Cryptography Standardization process. It is a code-based cryptosystem that enjoys a simple definition, well-understood underlying security, and interesting performance. The most critical step in this cryptosystem consists of correcting errors in a QC-MDPC linear code. The BIKE team proposed variants of the Bit-Flipping Decoder for this step for Round 1 and 2 of the standardization process. In this paper, we propose an alternative decoder which is more friendly to hardware implementations, leading to a latency-area performance comparable to the literature while introducing power side channel resilience. We also show that our design can accelerate all key generation, encapsulation and decapsulation operations using very few common logic building blocks.
Metadata
- Available format(s)
-
PDF
- Category
- Public-key cryptography
- Publication info
- Preprint.
- Keywords
- Post-Quantum CryptographyPQCBIKEQC-MDPCBit-flipping DecoderHardware AccelerationNIST PQC Standardization Project
- Contact author(s)
-
andrew h reinders @ intel com
rafael misoczki @ intel com
santosh ghosh @ intel com
manoj r sastry @ intel com - History
- 2020-02-06: received
- Short URL
- https://ia.cr/2020/117
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2020/117,
author = {Andrew Reinders and Rafael Misoczki and Santosh Ghosh and Manoj Sastry},
title = {Efficient {BIKE} Hardware Design with Constant-Time Decoder},
howpublished = {Cryptology {ePrint} Archive, Paper 2020/117},
year = {2020},
url = {https://eprint.iacr.org/2020/117}
}
