Cryptology ePrint Archive: Report 2020/1148

An Area Aware Accelerator for Elliptic Curve Point Multiplication

Malik Imran and Samuel Pagliarini and Muhammad Rashid

Abstract: This work presents a hardware accelerator, for the optimization of latency and area at the same time, to improve the performance of point multiplication process in Elliptic Curve Cryptography. In order to reduce the overall computation time in the proposed 2-stage pipelined architecture, a rescheduling of point addition and point doubling instructions is performed along with an efficient use of required memory locations. Furthermore, a 41-bit multiplier is also proposed. Consequently, the FPGA and ASIC implementation results have been provided. The performance comparison with state-of-the-art implementations, in terms of latency and area, proves the significance of the proposed accelerator.

Category / Keywords: public-key cryptography / elliptic curve cryptography, point multiplication, Montgomery algorithm, FPGA, ASIC

Date: received 21 Sep 2020

Contact author: malik imran at taltech ee,samuel pagliarini@taltech ee,mfelahi@uqu edu sa

Available format(s): PDF | BibTeX Citation

Version: 20200925:183511 (All versions of this report)

Short URL: ia.cr/2020/1148


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