Paper 2020/1125

High-Speed FPGA Implementation of SIKE Based on An Ultra-Low-Latency Modular Multiplier

Jing Tian, Bo Wu, and Zhongfeng Wang

Abstract

The supersingular isogeny key encapsulation (SIKE) protocol, as one of the post-quantum protocol candidates, is widely regarded as the best alternative for curve-based cryptography. However, the long latency, caused by the serial large-degree isogeny computation which is dominated by modular multiplications, has made it less competitive than most popular post-quantum candidates. In this paper, we propose a high-speed and low-latency architecture for our recently presented optimized SIKE algorithm. Firstly, we design a new field arithmetic logic unit (FALU) with many algorithmic transformations and architectural optimizations. Especially, for the FALU, an extremely low-latency modular multiplier is devised based on a modified algorithm by fully parallelizing and highly optimizing the small-size multipliers and the reduction submodules. Secondly, we develop a compact control logic and update the instructions based on the benchmark provided in the newest SIKE library, fitting well with our design. Thirdly, an efficient memory access method is proposed by scheduling the input and output of the arithmetic logic unit (ALU) in two identical RAMs, which can significantly reduce the latency. Finally, we code the proposed architectures using the Verilog language and integrate them into the SIKE library. The implementation results on a Xilinx Virtex-7 FPGA show that for SIKEp751, our design only costs 9.3 ms with a frequency of 155.8 MHz, about 2x faster than the state-of-the-art, and achieves the best area efficiency among existing works. Particularly, the modular multiplier merely needs 16 clock cycles, reducing the delay by nearly one order of magnitude with a small factor of increase in hardware resource.

Note: Figure 6 is further beautified; Figure 7 is corrected for the plus or minus signs of three adders.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published elsewhere. MINOR revision.IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
Modular multiplicationelliptic curve cryptography (ECC)post-quantum cryptography (PQC)hardware implementationFPGA.
Contact author(s)
tianjing @ nju edu cn
History
2021-08-04: last of 2 revisions
2020-09-21: received
See all versions
Short URL
https://ia.cr/2020/1125
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2020/1125,
      author = {Jing Tian and Bo Wu and Zhongfeng Wang},
      title = {High-Speed FPGA Implementation of SIKE Based on An Ultra-Low-Latency Modular Multiplier},
      howpublished = {Cryptology ePrint Archive, Paper 2020/1125},
      year = {2020},
      note = {\url{https://eprint.iacr.org/2020/1125}},
      url = {https://eprint.iacr.org/2020/1125}
}
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