Cryptology ePrint Archive: Report 2020/1067

A Constant Time Full Hardware Implementation of Streamlined NTRU Prime

Adrian Marotzke

Abstract: This paper presents a constant time hardware implementation of the NIST round 2 post-quantum cryptographic algorithm Streamlined NTRU Prime. We implement the entire KEM algorithm, including all steps for key generation, encapsulation and decapsulation, and all en- and decoding. We focus on optimizing the resources used, as well as applying optimization and parallelism available due to the hardware design. We show the core en- and decapsulation requires only a fraction of the total FPGA fabric resource cost, which is dominated by that of the hash function, and the en- and decoding algorithm. For the NIST Security Level 3, our implementation uses a total of 1841 slices on a Xilinx Zynq Ultrascale+ FPGA, together with 14 BRAMs and 19 DSPs. The maximum achieved frequency is 271 MHz, at which the key generation, encapsulation and decapsulation take 4808 μs, 524 μs and 958 μs respectively. To our knowledge, this work is the first full hardware implementation where the entire algorithm is implemented.

Category / Keywords: implementation / NTRU Prime Post-Quantum Cryptography FPGA Hardware VHDL Key Encapsulation Mechanism Lattice-based cryptography

Date: received 3 Sep 2020

Contact author: adrian marotzke at tuhh de

Available format(s): PDF | BibTeX Citation

Version: 20200903:091550 (All versions of this report)

Short URL: ia.cr/2020/1067


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