Paper 2020/040
A Compact and Scalable Hardware/Software Co-design of SIKE
Pedro Maat C. Massolino and Patrick Longa and Joost Renes and Lejla Batina
Abstract
We present efficient and compact hardware/software co-design implementations of the Supersingular Isogeny Key Encapsulation (SIKE) protocol on field-programmable gate arrays (FPGAs). In order to be better equipped for different post-quantum scenarios, our architectures were designed to feature high-flexibility by covering all the currently available parameter sets and with support for primes up to 1016 bits. In particular, any of the current SIKE parameters equivalent to the post-quantum security of AES-128/192/256 and SHA3-256 can be selected and run on-the-fly. This security scalability property, together with the small footprint and efficiency of our architectures, makes them ideal for embedded applications in a post-quantum world. In addition, the proposed implementations exhibit regular, constant-time execution, which provides protection against timing and simple side-channel attacks. Our results demonstrate that supersingular isogeny-based primitives such as SIDH and SIKE can indeed be deployed for embedded applications featuring competitive performance. For example, our smallest architecture based on a 128-bit MAC unit takes only 3415 slices, 21 BRAMs and 57 DSPs on a Virtex 7 690T and can perform key generation, encapsulation and decapsulation in 14.4, 24.4 and 26.0 milliseconds for SIKEp434 and in 52.3, 86.4 and 93.2 milliseconds for SIKEp751, respectively.
Metadata
- Available format(s)
- Category
- Implementation
- Publication info
- Published by the IACR in TCHES 2020
- Keywords
- Post-quantum cryptographysupersingular isogeniesSIDHSIKEhardwaresoftware co-designFPGAconstant-timeembedded applications
- Contact author(s)
-
P Massolino @ cs ru nl
plonga @ microsoft com
j r renes91 @ gmail com
lejla @ cs ru nl - History
- 2020-06-25: revised
- 2020-01-15: received
- See all versions
- Short URL
- https://ia.cr/2020/040
- License
-
CC BY