Paper 2019/802

New Circuit Minimization Techniques for Smaller and Faster AES SBoxes

Alexander Maximov and Patrik Ekdahl

Abstract

In this paper we consider various methods and techniques to find the smallest circuit realizing a given linear transformation on $n$ input signals and $m$ output signals, with a constraint of a maximum depth, $maxD$, of the circuit. Additional requirements may include that input signals can arrive to the circuit with different delays, and output signals may be requested to be ready at a different depth. We apply these methods and also improve previous results in order to find hardware circuits for forward, inverse, and combined AES SBoxes, and for each of them we provide the fastest and smallest combinatorial circuits. Additionally, we propose a novel technique with ``floating multiplexers'' to minimize the circuit for the combined SBox, where we have two different linear matrices (forward and inverse) combined with multiplexers. The resulting AES SBox solutions are the fastest and smallest to our knowledge.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Published by the IACR in Tches 2019
Keywords
AES SBoxcircuit areacircuit depthmultiplexerslinear matrices
Contact author(s)
patrik ekdahl @ ericsson com
History
2019-08-09: revised
2019-07-14: received
See all versions
Short URL
https://ia.cr/2019/802
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2019/802,
      author = {Alexander Maximov and Patrik Ekdahl},
      title = {New Circuit Minimization Techniques for Smaller and Faster AES SBoxes},
      howpublished = {Cryptology ePrint Archive, Paper 2019/802},
      year = {2019},
      note = {\url{https://eprint.iacr.org/2019/802}},
      url = {https://eprint.iacr.org/2019/802}
}
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