Cryptology ePrint Archive: Report 2019/802

New Circuit Minimization Techniques for Smaller and Faster AES SBoxes

Alexander Maximov and Patrik Ekdahl

Abstract: In this paper we consider various methods and techniques to find the smallest circuit realizing a given linear transformation on $n$ input signals and $m$ output signals, with a constraint of a maximum depth, $maxD$, of the circuit. Additional requirements may include that input signals can arrive to the circuit with different delays, and output signals may be requested to be ready at a different depth. We apply these methods and also improve previous results in order to find hardware circuits for forward, inverse, and combined AES SBoxes, and for each of them we provide the fastest and smallest combinatorial circuits. Additionally, we propose a novel technique with ``floating multiplexers'' to minimize the circuit for the combined SBox, where we have two different linear matrices (forward and inverse) combined with multiplexers. The resulting AES SBox solutions are the fastest and smallest to our knowledge.

Category / Keywords: implementation / AES SBox, circuit area, circuit depth, multiplexers, linear matrices

Original Publication (in the same form): IACR-CHES-2019

Date: received 11 Jul 2019, last revised 9 Aug 2019

Contact author: patrik ekdahl at ericsson com

Available format(s): PDF | BibTeX Citation

Version: 20190809:100835 (All versions of this report)

Short URL: ia.cr/2019/802


[ Cryptology ePrint archive ]