Efficient Cryptography on the RISC-V Architecture

Ko Stoffelen

Paper 2019/794

Efficient Cryptography on the RISC-V Architecture

Ko Stoffelen

Abstract

RISC-V is a promising free and open-source instruction set architecture. Most of the instruction set has been standardized and several hardware implementations are commercially available. In this paper we highlight features of RISC-V that are interesting for optimizing implementations of cryptographic primitives. We provide the first optimized assembly implementations of table-based AES, bitsliced AES, ChaCha, and the Keccak-$f$[1600] permutation for the RV32I instruction set. With respect to public-key cryptography, we study the performance of arbitrary-precision integer arithmetic without a carry flag. We then estimate the improvement that can be gained by several RISC-V extensions. These performance studies also serve to aid design choices for future RISC-V extensions and implementations.

Note: Fixed a wrong number in the HiFive1 specs

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. Latincrypt 2019
Keywords: RISC-V AES ChaCha Keccak arbitrary-precision arithmetic software optimization
Contact author(s): k stoffelen @ cs ru nl
History: 2019-07-15: revised; 2019-07-14: received; See all versions
Short URL: https://ia.cr/2019/794
License: CC BY

BibTeX

@misc{cryptoeprint:2019/794,
      author = {Ko Stoffelen},
      title = {Efficient Cryptography on the RISC-V Architecture},
      howpublished = {Cryptology ePrint Archive, Paper 2019/794},
      year = {2019},
      note = {\url{https://eprint.iacr.org/2019/794}},
      url = {https://eprint.iacr.org/2019/794}
}