Cryptology ePrint Archive: Report 2019/711

SIKE'd Up: Fast and Secure Hardware Architectures for Supersingular Isogeny Key Encapsulation

Brian Koziel and A-Bon Ackie and Rami El Khatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani

Abstract: In this work, we present a fast parallel architecture to perform supersingular isogeny key encapsulation (SIKE). We propose and implement a fast isogeny accelerator architecture that uses fast and parallelized isogeny formulas. On top of our isogeny accelerator, we build a novel architecture for the SIKE primitive, which provides both quantum and IND-CCA security. Since SIKE can support static keys, we propose and implement additional differential power analysis countermeasures. We synthesized this architecture on the Xilinx Artix-7, Virtex-7, and Kintex UltraScale+ FPGA families. Over Virtex-7 FPGA's, our constant-time implementations are roughly 14% faster than the state-of-the-art with a better area-time product. At the NIST security level 5 on a Kintex UltraScale+ FPGA, we can execute the entire SIKE protocol in 15.3 ms. This work continues to improve the speed of isogeny-based computations and also features all parameter sets of the SIKE round 2 specification, with results applicable to NIST's post-quantum standardization process.

Category / Keywords: implementation / SIKE, post-quantum cryptography isogeny-based cryptography, FPGA

Date: received 15 Jun 2019, last revised 11 Apr 2020

Contact author: razarderakhsh at fau edu, kozielbrian at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20200411:214553 (All versions of this report)

Short URL:

[ Cryptology ePrint archive ]