Paper 2019/711

SIKE'd Up: Fast and Secure Hardware Architectures for Supersingular Isogeny Key Encapsulation

Brian Koziel, A-Bon Ackie, Rami El Khatib, Reza Azarderakhsh, and Mehran Mozaffari-Kermani


In this work, we present a fast parallel architecture to perform supersingular isogeny key encapsulation (SIKE). We propose and implement a fast isogeny accelerator architecture that uses fast and parallelized isogeny formulas. On top of our isogeny accelerator, we build a novel architecture for the SIKE primitive, which provides both quantum and IND-CCA security. Since SIKE can support static keys, we propose and implement additional differential power analysis countermeasures. We synthesized this architecture on the Xilinx Artix-7, Virtex-7, and Kintex UltraScale+ FPGA families. Over Virtex-7 FPGA's, our constant-time implementations are roughly 14% faster than the state-of-the-art with a better area-time product. At the NIST security level 5 on a Kintex UltraScale+ FPGA, we can execute the entire SIKE protocol in 15.3 ms. This work continues to improve the speed of isogeny-based computations and also features all parameter sets of the SIKE round 2 specification, with results applicable to NIST's post-quantum standardization process.

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Preprint. MINOR revision.
Contact author(s)
razarderakhsh @ fau edu
kozielbrian @ gmail com
2020-04-11: last of 2 revisions
2019-06-18: received
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      author = {Brian Koziel and A-Bon Ackie and Rami El Khatib and Reza Azarderakhsh and Mehran Mozaffari-Kermani},
      title = {{SIKE}'d Up: Fast and Secure Hardware Architectures for Supersingular Isogeny Key Encapsulation},
      howpublished = {Cryptology ePrint Archive, Paper 2019/711},
      year = {2019},
      note = {\url{}},
      url = {}
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