Cryptology ePrint Archive: Report 2019/405

A Novel FPGA Architecture and Protocol for the Self-attestation of Configurable Hardware

Jo Vliegen and Md Masoom Rabbani and Mauro Conti and Nele Mentens

Abstract: Field-Programmable Gate Arrays or FPGAs are popular platforms for hardware-based attestation. They offer protection against physical and remote attacks by verifying if an embedded processor is running the intended application code. However, since FPGAs are configurable after deployment (thus not tamper-resistant), they are susceptible to attacks, just like microprocessors. Therefore, attesting an electronic system that uses an FPGA should be done by verifying the status of both the software and the hardware, without the availability of a dedicated tamper-resistant hardware module. Inspired by the work of Perito and Tsudik, this paper proposes a partially reconfigurable FPGA architecture and attestation protocol that enable the self-attestation of the FPGA. Through the use of our solution, the FPGA can be used as a trusted hardware module to perform hardware-based attestation of a processor. This way, an entire hardware/software system can be protected against malicious code updates.

Category / Keywords: implementation / FPGA, configurable hardware, remote attestation, hardware-based attestation, partial reconfiguration, ICAP, configuration readback

Original Publication (with major differences): SACHa: Self-Attestation of Configurable Hardware. In Proceedings of the Design Automation and Test in Europe Conference (DATE 2019)

Date: received 17 Apr 2019

Contact author: rabbani at math unipd it, nele mentens at kuleuven be

Available format(s): PDF | BibTeX Citation

Note: This submission is based on preliminary work by the same authors reported in the paper“SACHa: Self-Attestation of Configurable Hardware”- accepted in the Proceedings of the Design Automation and Test in Europe Conference(DATE’19).

Version: 20190422:184310 (All versions of this report)

Short URL:

[ Cryptology ePrint archive ]