### Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols (Extended Version)

Utsav Banerjee, Tenzin S. Ukyab, and Anantha P. Chandrakasan

##### Abstract

Public key cryptography protocols, such as RSA and elliptic curve cryptography, will be rendered insecure by Shor’s algorithm when large-scale quantum computers are built. Cryptographers are working on quantum-resistant algorithms, and lattice-based cryptography has emerged as a prime candidate. However, high computational complexity of these algorithms makes it challenging to implement lattice-based protocols on low-power embedded devices. To address this challenge, we present Sapphire – a lattice cryptography processor with configurable parameters. Efficient sampling, with a SHA-3-based PRNG, provides two orders of magnitude energy savings; a single-port RAM-based number theoretic transform memory architecture is proposed, which provides 124k-gate area savings; while a low-power modular arithmetic unit accelerates polynomial computations. Our test chip was fabricated in TSMC 40nm low-power CMOS process, with the Sapphire cryptographic core occupying 0.28 mm2 area consisting of 106k logic gates and 40.25 KB SRAM. Sapphire can be programmed with custom instructions for polynomial arithmetic and sampling, and it is coupled with a low-power RISC-V micro-processor to demonstrate NIST Round 2 lattice-based CCA-secure key encapsulation and signature protocols Frodo, NewHope, qTESLA, CRYSTALS-Kyber and CRYSTALS-Dilithium, achieving up to an order of magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations. All key building blocks of Sapphire are constant-time and secure against timing and simple power analysis side-channel attacks. We also discuss how masking-based DPA countermeasures can be implemented on the Sapphire core without any changes to the hardware.

##### Metadata
Available format(s)
Category
Implementation
Publication info
A major revision of an IACR publication in TCHES 2019
DOI
10.13154/tches.v2019.i4.17-61
Keywords
hardware implementationlattice-based cryptographypost-quantum
Contact author(s)
utsav @ mit edu
History
2020-09-20: last of 5 revisions
2019-10-03: received
See all versions
Short URL
https://ia.cr/2019/1140
License

CC BY

BibTeX

@misc{cryptoeprint:2019/1140,
author = {Utsav Banerjee and Tenzin S.  Ukyab and Anantha P.  Chandrakasan},
title = {Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols (Extended Version)},
howpublished = {Cryptology ePrint Archive, Paper 2019/1140},
year = {2019},
doi = {10.13154/tches.v2019.i4.17-61},
note = {\url{https://eprint.iacr.org/2019/1140}},
url = {https://eprint.iacr.org/2019/1140}
}

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