Paper 2019/1040
Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators
Abhishek Chakraborty and Ankur Srivastava
Abstract
Existing logic obfuscation approaches aim to protect hardware design IPs from SAT attack by increasing query count and output corruptibility of a locked netlist. In this paper, we demonstrate the ineffectiveness of such techniques to obfuscate hardware accelerator platforms. Subsequently, we propose a Hardware/software co-design based Accelerator Obfuscation (HSCAO) scheme to provably safeguard the IP of such designs against SAT as well as removal/bypass type of attacks while still maintaining high output corruptability for applications. The attack resiliency of HSCAO scheme is manifested by using a sequence of keys to obfuscate instruction encoding for an application. Experimental evaluations utilizing an accelerator simulator demonstrate the effectiveness of our proposed countermeasure.
Note: Personal use only. Published in IEEE Computer Society Annual Symposium on VLSI 2019
Metadata
- Available format(s)
-
PDF
- Category
- Implementation
- Publication info
- Published elsewhere. IEEE Computer Society Annual Symposium on VLSI 2019
- Keywords
- hardware securitylogic obfuscationhardware accelerator
- Contact author(s)
- abhi1990 @ terpmail umd edu
- History
- 2019-09-18: received
- Short URL
- https://ia.cr/2019/1040
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2019/1040,
author = {Abhishek Chakraborty and Ankur Srivastava},
title = {Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators},
howpublished = {Cryptology {ePrint} Archive, Paper 2019/1040},
year = {2019},
url = {https://eprint.iacr.org/2019/1040}
}
