Cryptology ePrint Archive: Report 2019/1040

Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators

Abhishek Chakraborty and Ankur Srivastava

Abstract: Existing logic obfuscation approaches aim to protect hardware design IPs from SAT attack by increasing query count and output corruptibility of a locked netlist. In this paper, we demonstrate the ineffectiveness of such techniques to obfuscate hardware accelerator platforms. Subsequently, we propose a Hardware/software co-design based Accelerator Obfuscation (HSCAO) scheme to provably safeguard the IP of such designs against SAT as well as removal/bypass type of attacks while still maintaining high output corruptability for applications. The attack resiliency of HSCAO scheme is manifested by using a sequence of keys to obfuscate instruction encoding for an application. Experimental evaluations utilizing an accelerator simulator demonstrate the effectiveness of our proposed countermeasure.

Category / Keywords: implementation / hardware security, logic obfuscation, hardware accelerator

Original Publication (in the same form): IEEE Computer Society Annual Symposium on VLSI 2019

Date: received 12 Sep 2019

Contact author: abhi1990 at terpmail umd edu

Available format(s): PDF | BibTeX Citation

Note: Personal use only. Published in IEEE Computer Society Annual Symposium on VLSI 2019

Version: 20190918:122709 (All versions of this report)

Short URL: ia.cr/2019/1040


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