Cryptology ePrint Archive: Report 2018/656

FPGA Cluster based high performance Cryptanalysis framework

Abhishek Bajpai and S V Kulgod

Abstract: In this paper a ‘FPGA cluster’ based framework for high performance Cryptanalysis has been proposed. The framework abstracts underlying networked FPGA cluster into a unified acceleration resource. It does so by implementing requested amount of computation kernels (cryptographic modules) and managing efficient distribution of the network band-width between the inter-FPGA and intra-FPGA computation kernels. Further agile methodology for developing such networked computation kernels with use of a high level language (Python) based HDL library and seamless integration with a user space crypt analysis application have been discussed. 40-bit partial key attack over AES256 has been demonstrated as a capability demonstration. Performance higher than clustered CPUs and GPUs at lower costs and power is reported.

Category / Keywords: implementation /

Original Publication (with minor differences): www.researchgate.net (Preprint)
DOI:
DOI: 10.13140/RG.2.2.34006.55364

Date: received 6 Jul 2018

Contact author: abbajpai at barc gov in

Available format(s): PDF | BibTeX Citation

Version: 20180706:221806 (All versions of this report)

Short URL: ia.cr/2018/656


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