High-speed Side-channel-protected Encryption and Authentication in Hardware

Nele Mentens; Vojtech Miskovsky; Martin Novotny; Jo Vliegen

Paper 2018/1088

High-speed Side-channel-protected Encryption and Authentication in Hardware

Nele Mentens, Vojtech Miskovsky, Martin Novotny, and Jo Vliegen

Abstract

This paper describes two FPGA implementations for the encryption and authentication of data, based on the AES algorithm running in Galois/Counter mode (AES-GCM). Both architectures are protected against side-channel analysis attacks through the use of a threshold implementation (TI). The first architecture is fully unrolled and optimized for throughput. The second architecture uses a round-based structure, fits on a relatively small FPGA board, and is evaluated for side-channel attack resistance. We perform a Test Vector Leakage Assessment (TVLA), which shows no first-order leakage in the power consumption of the FPGA. To the best of our knowledge, our work is (1) the first to describe a throughput-optimized FPGA architecture of AES-GCM, protected against first-order side-channel information leakage, and (2) the first to evaluate the side-channel attack resistance of a TI-protected AES-GCM implementation.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. Major revision. 2018 IEEE 3rd International Verification and Security Workshop (IVSW)
Keywords: AES Galois Counter Mode (GCM)FPGA Threshold Implementation (TI)Test Vector Leakage Assessment (TVLA)
Contact author(s): nele mentens @ kuleuven be
History: 2018-11-09: received
Short URL: https://ia.cr/2018/1088
License: CC BY

BibTeX

@misc{cryptoeprint:2018/1088,
      author = {Nele Mentens and Vojtech Miskovsky and Martin Novotny and Jo Vliegen},
      title = {High-speed Side-channel-protected Encryption and Authentication in Hardware},
      howpublished = {Cryptology {ePrint} Archive, Paper 2018/1088},
      year = {2018},
      url = {https://eprint.iacr.org/2018/1088}
}