Cryptology ePrint Archive: Report 2017/621

Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks

Xiaolin Xu and Bicky Shakya and Mark M. Tehranipoor and Domenic Forte

Abstract: Logic locking has emerged as a promising technique for protecting gate-level semiconductor intellectual property. However, recent work has shown that such gate-level locking techniques are vulnerable to Boolean satisfiability (SAT) attacks. In order to thwart such attacks, several SAT-resistant logic locking techniques have been proposed, which minimize the discriminating ability of input patterns to rule out incorrect keys. In this work, we show that such SAT-resistant logic locking techniques have their own set of unique vulnerabilities. In particular, we propose a novel ``bypass attack" that ensures the locked circuit works even when an incorrect key is applied. Such a technique makes it possible for an adversary to be oblivious to the type of SAT-resistant protection applied on the circuit, and still be able to restore the circuit to its correct functionality. We show that such a bypass attack is feasible on a wide range of benchmarks and SAT-resistant techniques, while incurring minimal run-time and area/delay overhead. Binary decision diagrams (BDDs) are utilized to analyze the proposed bypass attack and assess tradeoffs in security vs overhead of various countermeasures.

Category / Keywords: Logic Locking; SAT Attack; Hardware IP Protection; Hardware Security

Original Publication (with minor differences): IACR-CHES-2017

Date: received 26 Jun 2017

Contact author: xiaolinxu at ece ufl edu

Available format(s): PDF | BibTeX Citation

Version: 20170627:192555 (All versions of this report)

Short URL: ia.cr/2017/621

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