### Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks

Xiaolin Xu, Bicky Shakya, Mark M. Tehranipoor, and Domenic Forte

##### Abstract

Logic locking has emerged as a promising technique for protecting gate-level semiconductor intellectual property. However, recent work has shown that such gate-level locking techniques are vulnerable to Boolean satisfiability (SAT) attacks. In order to thwart such attacks, several SAT-resistant logic locking techniques have been proposed, which minimize the discriminating ability of input patterns to rule out incorrect keys. In this work, we show that such SAT-resistant logic locking techniques have their own set of unique vulnerabilities. In particular, we propose a novel bypass attack" that ensures the locked circuit works even when an incorrect key is applied. Such a technique makes it possible for an adversary to be oblivious to the type of SAT-resistant protection applied on the circuit, and still be able to restore the circuit to its correct functionality. We show that such a bypass attack is feasible on a wide range of benchmarks and SAT-resistant techniques, while incurring minimal run-time and area/delay overhead. Binary decision diagrams (BDDs) are utilized to analyze the proposed bypass attack and assess tradeoffs in security vs overhead of various countermeasures.

Available format(s)
Publication info
A minor revision of an IACR publication in CHES 2017
Keywords
Logic LockingSAT AttackHardware IP ProtectionHardware Security
Contact author(s)
xiaolinxu @ ece ufl edu
History
Short URL
https://ia.cr/2017/621

CC BY

BibTeX

@misc{cryptoeprint:2017/621,
author = {Xiaolin Xu and Bicky Shakya and Mark M.  Tehranipoor and Domenic Forte},
title = {Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks},
howpublished = {Cryptology ePrint Archive, Paper 2017/621},
year = {2017},
note = {\url{https://eprint.iacr.org/2017/621}},
url = {https://eprint.iacr.org/2017/621}
}
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