SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA

Maik Ender; Alexander Wild; Amir Moradi

Paper 2017/284

SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA

Maik Ender, Alexander Wild, and Amir Moradi

Abstract

Side-channel analysis attacks, particularly power analysis attacks, have become one of the major threats, that hardware designers have to deal with. To defeat them, the majority of the known concepts are based on either masking, hiding, or rekeying (or a combination of them). This work deals with a hiding scheme, more precisely a power-equalization technique which is ideally supposed to make the amount of power consumption of the device independent of its processed data. We propose and practically evaluate a novel construction dedicated to Xilinx FPGAs, which rules out the state of the art with respect to the achieved security level and the resource overhead.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. COSADE 2017
Keywords: side-channel analysis countermeasure
Contact author(s): maik ender @ rub de
History: 2017-03-30: received
Short URL: https://ia.cr/2017/284
License: CC BY

BibTeX

@misc{cryptoeprint:2017/284,
      author = {Maik Ender and Alexander Wild and Amir Moradi},
      title = {{SafeDRP}: Yet Another Way Toward Power-Equalized Designs in {FPGA}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2017/284},
      year = {2017},
      url = {https://eprint.iacr.org/2017/284}
}