Cryptology ePrint Archive: Report 2017/1261

A Comprehensive Performance Analysis of Hardware Implementations of CAESAR Candidates

Sachin Kumar and Jawad Haj-Yahya and Mustafa Khairallah and Mahmoud A. Elmohr and Anupam Chattopadhyay

Abstract: Authenticated encryption with Associated Data (AEAD) plays a significant role in cryptography because of its ability to provide integrity, confidentiality and authenticity at the same time. Due to the emergence of security at the edge of computing fabric, such as, sensors and smartphone devices, there is a growing need of lightweight AEAD ciphers. Currently, a worldwide contest, titled CAESAR, is being held to decide on a set of AEAD ciphers, which are distinguished by their security, run-time performance, energy-efficiency and low area budget. For accurate evaluation of CAESAR candidates, it is of utmost importance to have independent and thorough optimization for each of the ciphers both for their corresponding hardware and software implementations.

In this paper, we have carried out an evaluation of the optimized hardware implementation of AEAD ciphers selected in CAESAR third round. We specifically focus on manual optimization of the micro-architecture, evaluations for ASIC technology libraries and the effect of CAESAR APIs on the performances. While these has been studied for FPGA platforms and standalone cipher implementation - to the best of our knowledge, this is the first detailed ASIC benchmarking of CAESAR candidates including manual optimization. In this regard, we benchmarked all prior reported designs, including the code generated by high-level synthesis flows.

Detailed optimization studies are reported for NORX, CLOC and Deoxys-I. Our pre-layout results using commercial ASIC technology library and synthesis tools show that optimized NORX is 40.81% faster and 18.02% smaller, optimized CLOC is 38.30% more energy efficient and 20.65% faster and optimized Deoxys-I is 35.16% faster, with respect to the best known results. Similar or better performance results are also achieved for FPGA platforms.

Category / Keywords: implementation / ASIC Implementation, FPGA, Authenticated Encryption, Logic Optimization, Technology Mapping

Date: received 25 Dec 2017, last revised 7 May 2018

Contact author: mustafam001 at e ntu edu sg,sachinkumar@ntu edu sg,jawad@ntu edu sg, anupam@ntu edu sg

Available format(s): PDF | BibTeX Citation

Version: 20180508:033020 (All versions of this report)

Short URL: ia.cr/2017/1261

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