Paper 2016/966

High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m)

Bahram Rashidi, Sayed Masoud Sayedi, and Reza Rezaeian Farashahi

Abstract

In this paper, by employing the logical effort technique an efficient and high-speed VLSI implementation of the digit-serial Gaussian normal basis multiplier is presented. It is constructed by using AND, XOR and XOR tree components. To have a low-cost implementation with low number of transistors, the block of AND gates are implemented by using NAND gates based on the property of the XOR gates in the XOR tree. To optimally decrease the delay and increase the drive ability of the circuit the logical effort method as an efficient method for sizing the transistors is employed. By using this method and also a 4-input XOR gate structure, the circuit is designed for minimum delay. The digit-serial Gaussian normal basis multiplier is implemented over two binary finite fields GF(2163) and GF(2233) in 0.18μm CMOS technology for three different digit sizes. The results show that the proposed structures, compared to previous structures, have been improved in terms of delay and area parameters.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint. MINOR revision.
Contact author(s)
b_rashidi86 @ yahoo com
History
2016-10-10: received
Short URL
https://ia.cr/2016/966
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2016/966,
      author = {Bahram Rashidi and Sayed Masoud Sayedi and Reza Rezaeian Farashahi},
      title = {High-speed {VLSI} implementation of Digit-serial Gaussian normal basis Multiplication over {GF}(2m)},
      howpublished = {Cryptology {ePrint} Archive, Paper 2016/966},
      year = {2016},
      url = {https://eprint.iacr.org/2016/966}
}
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