Paper 2016/725

Tile-Based Modular Architecture for Accelerating Homomorphic Function Evaluation on FPGA

Mustafa Khairallah and Maged Ghoneima

Abstract

In this paper, a new architecture for accelerating homomorphic function evaluation on FPGA is proposed. A parallel cached NTT algorithm with an overall time complexity O(sqrt(N)log(sqrt(N)) is presented. The architecture has been implemented on Xilinx Virtex 7 XC7V1140T FPGA. achieving a 60% utilization ratio. The implementation performs 32-bit 2^(16)-point NTT algorithm in 23.8 us, achieving speed-up of 2x over the state of the art architectures. The architecture has been evaluated by computing a block of each of the AES and SIMON-64/128 on the LTV and YASHE schemes. The proposed architecture can evaluate the AES circuit using the LTV scheme in 4 minutes, processing 2048 blocks in parallel, which leads to an amortized performance of 117 ms/block, which is the fastest performance reported to the best of our knowledge.

Metadata
Available format(s)
PDF
Publication info
Published elsewhere. Major revision. 2016 IEEE 59th International Midwest Symposium on Circuits and Systems
Keywords
FHEHomomorphicFPGAVirtexNTTCRT
Contact author(s)
khairallah @ ieee org
History
2016-07-31: revised
2016-07-27: received
See all versions
Short URL
https://ia.cr/2016/725
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2016/725,
      author = {Mustafa Khairallah and Maged Ghoneima},
      title = {Tile-Based Modular Architecture for Accelerating Homomorphic Function Evaluation on FPGA},
      howpublished = {Cryptology ePrint Archive, Paper 2016/725},
      year = {2016},
      note = {\url{https://eprint.iacr.org/2016/725}},
      url = {https://eprint.iacr.org/2016/725}
}
Note: In order to protect the privacy of readers, eprint.iacr.org does not use cookies or embedded third party content.