A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version)

Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, and Jean-Luc Danger

Abstract

Testing of electronic components is indispensable to minimize malfunction and failure of complex electronic systems. Currently, functionality and performance of these electronic components are the main parameters tested. However, validation of performance is not enough when the applications are safety or security critical. Therefore the security and trust of devices must also be tested before validation for such applications. In this paper, we promote the use of On-Chip Power noise Measurements (OCM), in order to test security using side-channel techniques. We then propose for the first time a standard side-channel measurement setup using OCM. Finally, we provide some key ideas on methodology to integrate the validation of hardware security and trust in the standard testing flow, exploiting OCM.

Metadata
Available format(s)
Category
Applications
Publication info
Published elsewhere. MINOR revision.The 20th Asia and South Pacific Design Automation Conference
DOI
10.1109/ASPDAC.2015.7059100
Keywords
securitytruststandardised side-channel measurementhardware trojan
Contact author(s)
sbhasin @ ntu edu sg
History
2016-05-29: received
Short URL
https://ia.cr/2016/522
License

CC BY

BibTeX

@misc{cryptoeprint:2016/522,
author = {Daisuke Fujimoto and Shivam Bhasin and Makoto Nagata and Jean-Luc Danger},
title = {A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version)},
howpublished = {Cryptology ePrint Archive, Paper 2016/522},
year = {2016},
doi = {10.1109/ASPDAC.2015.7059100},
note = {\url{https://eprint.iacr.org/2016/522}},
url = {https://eprint.iacr.org/2016/522}
}

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