Paper 2016/441

Fault Tolerant Implementations of Delay-based Physically Unclonable Functions on FPGA

Durga Prasad Sahoo, Sikhar Patranabis, Debdeep Mukhopadhyay, and Rajat Subhra Chakraborty

Abstract

Recent literature has demonstrated that the security of Physically Unclonable Function (PUF) circuits might be adversely affected by the introduction of faults. In this paper, we propose novel and efficient architectures for a variety of widely used delay-based PUFs which are robust against high precision laser fault attacks proposed by Tajik et al. in FDTC-2015. The proposed architectures can be used to detect run-time modifications in the PUF design due to fault injection. In addition, we propose fault recovery techniques based on either logical reconfiguration or dynamic partial reconfiguration of the PUF design. We validate the robustness of our proposed fault tolerant delay-based PUF designs on Xilinx Artix-7 FPGA platform.

Metadata
Available format(s)
PDF
Category
Implementation
Publication info
Preprint. MAJOR revision.
Keywords
Arbiter PUF (APUF)PUFlaser fault attacks and countermeasuresrobust PUF architectures.
Contact author(s)
dpsahoo cs @ gmail com
History
2016-05-04: received
Short URL
https://ia.cr/2016/441
License
Creative Commons Attribution
CC BY

BibTeX

@misc{cryptoeprint:2016/441,
      author = {Durga Prasad Sahoo and Sikhar Patranabis and Debdeep Mukhopadhyay and Rajat Subhra Chakraborty},
      title = {Fault Tolerant Implementations of Delay-based Physically Unclonable Functions on FPGA},
      howpublished = {Cryptology ePrint Archive, Paper 2016/441},
      year = {2016},
      note = {\url{https://eprint.iacr.org/2016/441}},
      url = {https://eprint.iacr.org/2016/441}
}
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