### Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series

##### Abstract

Since 2012, it is publicly known that the bitstream encryption feature of modern Xilinx FPGAs can be broken by side-channel analysis. Presented at CT-RSA 2012, using graphics processing units (GPUs) the authors demonstrated power analysis attacks mounted on side-channel evaluation boards optimized for power measurements. In this work, we extend such attacks by moving to the EM side channel to examine their practical relevance in real-world scenarios. Furthermore, by following a certain measurement procedure we reduce the search space of each part of the attack from 2^{32} to 2^8, which allows mounting the attacks on ordinary workstations. Several Xilinx FPGAs from different families - including the 7 series devices - are susceptible to the attacks presented here.

Note: There is an error in normalization of Fisher's transform formula (pointed by Manuel Ilg <manuel.ilg@aisec.fraunhofer.de>) in Springer version of the paper. Here it is corrected.

Available format(s)
Category
Implementation
Publication info
DOI
10.1007/978-3-319-43283-0_5
Keywords
side-channel analysis
Contact author(s)
History
2017-04-01: revised
See all versions
Short URL
https://ia.cr/2016/249

CC BY

BibTeX

@misc{cryptoeprint:2016/249,
author = {Amir Moradi and Tobias Schneider},
title = {Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series},
howpublished = {Cryptology ePrint Archive, Paper 2016/249},
year = {2016},
doi = {10.1007/978-3-319-43283-0_5},
note = {\url{https://eprint.iacr.org/2016/249}},
url = {https://eprint.iacr.org/2016/249}
}

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