Paper 2016/057

On the Architectural Analysis of Arbiter Delay PUF Variants

DURGA PRASAD SAHOO, PHUONG HA NGUYEN, RAJAT SUBHRA CHAKRABORTY, and DEBDEEP MUKHOPADHYA

Abstract

The Arbiter Physically Unclonable Function (APUF) is a widely used strong delay PUF design. There are two FPGA variants of this design, namely, Programmable Delay Line APUF (PAPUF) and Double APUF (DAPUF) to mitigate the FPGA platform specific implementation issues. In this paper, we introduce the idea of Architectural Bias to compare the impact of the architecture of these APUF designs on their design bias. The biased challenge-response behavior of a delay PUF implies the non-uniform distributions of 0’s and 1’s in its response, and if this bias is due to the architectural issue of the PUF design, then it is called “Architectural Bias”. Another important source of bias is the implementation issue specific to an implementation platform. According to our study, a good PUF architecture results in PUF instances with a small amount of architectural bias. In this paper, we provide a comparison of APUF, PAPUF, and DAPUF based on their architectural bias values. In addition, we also compare these APUF architectures with respect to fulfilling the Strict Avalanche Criterion (SAC) and robustness against the machine learning (ML) based modeling attack. We validate our theoretical findings with Matlab based simulations, and the results reveal that the classic APUF has the least architectural bias, followed by DAPUF and PAPUF, respectively. We also conclude from the experimental results that the SAC property of DAPUF is better than that of APUF and PAPUF, and PAPUF’s SAC property is significantly poor. However, our analyses indicate that these APUF variants are vulnerable to ML-based modeling attack.