Cryptology ePrint Archive: Report 2015/348

A Hardware-based Countermeasure to Reduce Side-Channel Leakage - Design, Implementation, and Evaluation

An­dre­as Gor­nik and Amir Mo­ra­di and Jür­gen Oehm and Chris­tof Paar

Abstract: Side-channel attacks are one of the major concerns for security-enabled applications as they make use of information leaked by the physical implementation of the underlying cryptographic algorithm. Hence, reducing the side-channel leakage of the circuits realizing the cryptographic primitives is amongst the main goals of circuit designers. In this work we present a novel circuit concept, which decouples the main power supply from an internal power supply that is used to drive a single logic gate. The decoupling is done with the help of buffering capacitances integrated into semiconductor. We also introduce – compared to the previously known schemes – an improved decoupling circuit which reduces the crosstalk from the internal to the external power supply. The result of practical side-channel evaluation on a prototype chip fabricated in a 150nm CMOS technology shows a high potential of our proposed technique to reduce the side-channel leakages.

Category / Keywords: implementation / side-channel analysis, side-channel countermeasure, circuit-level countermeasure, ASIC, hardware-based countermeasure

Original Publication (in the same form): IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DOI: 10.1109/TCAD.2015.2423274

Date: received 19 Apr 2015, last revised 25 Apr 2015

Contact author: amir moradi at rub de

Available format(s): PDF | BibTeX Citation

Version: 20150425:065747 (All versions of this report)

Short URL: ia.cr/2015/348