Paper 2015/116

Efficient Hardware Design for Computing Pairings Using Few FPGA In-built DSPs

Riadh Brinci, Walid Khmiri, Mefteh Mbarek, Abdellatif Ben Rabâa, and Ammar Bouallègue


This paper is devoted to the design of a 258-bit multiplier for computing pairings over Barreto-Naehrig (BN) curves at 128-bit security level. The proposed design is optimized for Xilinx field programmable gate array (FPGA). Each 258-bit integer is represented as a polynomial with five, 65 bit signed integer, coefficients. Exploiting this splitting we designed a pipelined 65-bit multiplier based on new Karatsuba- Ofman variant using non-standard splitting to fit to the Xilinx embedded digital signal processor (DSP) blocks. We prototype the coprocessor in two architectures pipelined and serial on a Xilinx Virtex-6 FPGA using around 17000 slices and 11 DSPs in the pipelined design and 7 DSPs in the serial. The pipelined 128-bit pairing is computed in 1. 8 ms running at 225MHz and the serial is performed in 2.2 ms running at 185MHz. To the best of our knowledge, this implementation outperforms all reported hardware designs in term of DSP use. Keywords-

Available format(s)
Publication info
Pairing based CryptographyFPGAModular integer polynomial MultiplicationNon-Standard SplittingPairing-Friendly CurvesBN curveoptimal pairing
Contact author(s)
br riadh @ gmail com
2015-02-24: received
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Creative Commons Attribution


      author = {Riadh Brinci and Walid Khmiri and Mefteh Mbarek and Abdellatif Ben Rabâa and Ammar Bouallègue},
      title = {Efficient Hardware Design for Computing Pairings Using Few FPGA In-built DSPs},
      howpublished = {Cryptology ePrint Archive, Paper 2015/116},
      year = {2015},
      note = {\url{}},
      url = {}
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