Cryptology ePrint Archive: Report 2014/800

Efficient Pairings and ECC for Embedded Systems

Thomas Unterluggauer and Erich Wenger

Abstract: The research on pairing-based cryptography brought forth a wide range of protocols interesting for future embedded applications. One significant obstacle for the widespread deployment of pairing-based cryptography are its tremendous hardware and software requirements. In this paper we present three side-channel protected hardware/software designs for pairing-based cryptography yet small and practically fast: our plain ARM Cortex-M0+-based design computes a pairing in less than one second. The utilization of a multiply-accumulate instruction-set extension or a light-weight drop-in hardware accelerator that is placed between CPU and data memory improves runtime up to six times. With a 10.1 kGE large drop-in module and a 49 kGE large platform, our design is one of the smallest pairing designs available. Its very practical runtime of 162 ms for one pairing on a 254-bit BN curve and its reusability for other elliptic-curve based crypto systems offer a great solution for every microprocessor-based embedded application.

Category / Keywords: implementation

Original Publication (with minor differences): IACR-CHES-2014

Date: received 6 Oct 2014, last revised 23 Sep 2015

Contact author: thomas unterluggauer at iaik tugraz at

Available format(s): PDF | BibTeX Citation

Note: Added footnote reference to published source code at

Version: 20150923:140038 (All versions of this report)

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