Cryptology ePrint Archive: Report 2014/454

Early Propagation and Imbalanced Routing, How to Diminish in FPGAs

Amir Moradi and Vincent Immler

Abstract: This work deals with DPA-resistant logic styles, i.e., cell-level countermeasures against power analysis attacks that are known as a serious threat to cryptographic devices. Early propagation and imbalanced routings are amongst the well-known issues of such countermeasures, that - if not considered during the design process - can cause the underlying cryptographic device to be vulnerable to certain attacks. Although most of the DPA-resistant logic styles target an ASIC design process, there are a few attempts to apply them in an FPGA platform. This is due to the missing freedom in FPGA design tools required to deal with the aforementioned problems. Our contribution in this work is to provide solutions for both early propagation and imbalanced routings considering a modern Xilinx FPGA as the target platform. Foremost, based on the WDDL concept we design a new FPGA-based logic style without early propagation in both precharge and evaluation phases. Additionally, with respect to the limited routing resources within an FPGA we develop a customized router to nd the best appropriate dual-rail routes for a given dual-rail circuit. Based on practical experiments on a Virtex-5 FPGA our evaluations verify the efficiency of each of our proposed approaches. They significantly improve the resistance of the design compared to cases not benefiting from our schemes.

Category / Keywords: implementation / side-channel analysis, DPA countermeasure, dual-rail precharge logic, WDDL, FPGA

Original Publication (in the same form): IACR-CHES-2014

Date: received 12 Jun 2014, last revised 4 Apr 2016

Contact author: amir moradi at rub de

Available format(s): PDF | BibTeX Citation

Version: 20160404:073713 (All versions of this report)

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