### Side-Channel Leakage through Static Power – Should We Care about in Practice? –

##### Abstract

By shrinking the technology static power consumption of CMOS circuits is becoming a major concern. In this paper, we present the first practical results of exploiting static power consumption of FPGA-based cryptographic devices in order to mount a key-recovery side-channel attack. The experiments represented here are based on three Xilinx FPGAs built on 65nm, 45nm, and 28nm process technologies. By means of a sophisticated measurement setup and methodology we demonstrate an exploitable information leakage through static power of the underlying FPGAs. The current work highlights the feasibility of side-channel analysis attacks by static power that have been known for years but have not been performed and investigated in practice yet. This is a starting point for further research investigations, and may have a significant impact on the efficiency of DPA countermeasures in the near future.

Available format(s)
Category
Implementation
Publication info
A minor revision of an IACR publication in CHES 2014
Keywords
Side-Channel AnalysisStaic Power Consumption
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History
2014-07-08: last of 3 revisions
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Short URL
https://ia.cr/2014/025

CC BY

BibTeX

@misc{cryptoeprint:2014/025,