Cryptology ePrint Archive: Report 2013/461

HPAZ: a High-throughput Pipeline Architecture of ZUC in Hardware

Zongbin Liu and Neng Gao and Jiwu Jing and Peng Liu

Abstract: Abstract.In this paper, we propose a high-throughput pipeline architecture of the stream cipher ZUC which has been included in the security portfolio of 3GPP LTE-Advanced. In the literature, the schema with the highest throughput only implements the working stage of ZUC. The schemas which implement ZUC completely can only achieve a much lower throughput, since a self-feedback loop in the critical path significantly reduces operating frequency. In this paper we design a mixed two-stage pipeline architecture which not only completely implements ZUC but also significantly raises the throughput. We have imple-mented our architecture on FPGA and ASIC. On FPGA platform, the new architecture increases the throughput by 45%, compared with the latest work, and particularly the new architecture also saves nearly 12% of hardware resource. On 65nm ASIC technology, the throughput of the new design can up to 80Gbps, which is 2.7 times faster than the fastest one in the literature, in particularly, it also saves at least 40% of hardware resource. In addition to the academic design, compared with the fastest commercial design, the new architecture doubles the throughput of that. To the best of our knowledge, this evaluation result is so far the best outcome. It can be assumed that hardware implementations of ZUC following our architecture will fit in future LTE equipments better

Category / Keywords: implementation / Stream Cipher, FPGA, Hardware evaluation, ZUC

Date: received 25 Jul 2013, last revised 1 Aug 2013

Contact author: liuufo85 at gmail com

Available format(s): PDF | BibTeX Citation

Version: 20130801:090722 (All versions of this report)

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