Cryptology ePrint Archive: Report 2013/294

Synchronous Sampling and Clock Recovery of Internal Oscillators for Side Channel Analysis

Colin O'Flynn and Zhizhang (David) Chen

Abstract: Measuring power consumption for side-channel analysis typically uses an oscilloscope, which measures the data relative to an internal sample clock. By synchronizing the sampling clock to the clock of the target device, the sample rate requirements are considerably relaxed; the attack will succeed with a much lower sample rate.

This work measures the performance of a synchronous sampling system attacking a modern microcontroller running a software AES implementation. This attack is characterized under four conditions: with a stable crystal-oscillator based clock, with a clock that is randomly varied between 3.9 MHz - 13 MHz, with an internal oscillator that is randomly varied between 7.2 MHz - 8.1 MHz, and with an internal oscillator that has slight random variation due to natural `drift' in the oscillator.

Traces captured with the synchronous sampling technique can be processed with a standard Differential Power Analysis (DPA) style attack in all four cases, whereas when an oscilloscope is used only the stable oscillator setup is successful. This work also develops the hardware to recover the internal clock of a device which does not have an externally available clock. It is possible to implement this scheme in software only, allowing it to work with existing oscilloscope-based test environments.

Category / Keywords: implementation / side-channel analysis, acquisition, synchronization, DPA

Original Publication (in the same form): Journal of Cryptographic Engineering (JCEN)

Date: received 16 May 2013, last revised 20 Oct 2014

Contact author: coflynn at newae com

Available format(s): PDF | BibTeX Citation

Note: Update PDF to fix small errors, add note that final version will be available on

Version: 20141020:170538 (All versions of this report)

Short URL:

[ Cryptology ePrint archive ]