Paper 2012/535

A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function Grøstl

Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, and Teppei Yamazaki


This article describes the design of an 8-bit coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl on several Xilinx FPGAs. Our Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grøstl at all levels of security. Thanks to a careful organization of AES and Grøstl internal states in the register file, we manage to generate all read and write addresses by means of a modulo-128 counter and a modulo-256 counter. A fully autonomous implementation of Grøstl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput. Assuming that the security guarantees of Grøstl are at least as good as the ones of the other SHA-3 finalists, our results show that Grøstl is the best candidate for low-area cryptographic coprocessors.

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Published elsewhere. Unknown where it was published
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jeanluc beuchat @ gmail com
2012-09-20: revised
2012-09-20: received
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      author = {Nuray At and Jean-Luc Beuchat and Eiji Okamoto and Ismail San and Teppei Yamazaki},
      title = {A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function Grøstl},
      howpublished = {Cryptology ePrint Archive, Paper 2012/535},
      year = {2012},
      note = {\url{}},
      url = {}
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