Cryptology ePrint Archive: Report 2012/368

Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs

Kris Gaj and Ekawat Homsirikamol and Marcin Rogawski and Rabia Shahid and Malik Umar Sharif

Abstract: In this paper we present a comprehensive comparison of all Round 3 SHA-3 candidates and the current standard SHA-2 from the point of view of hardware performance in modern FPGAs. Each algorithm is implemented using multiple architectures based on the concepts of iteration, folding, unrolling, pipelining, and circuit replication. Trade-offs between speed and area are investigated, and the best architecture from the point of view of the throughput to area ratio is identified. Finally, all algorithms are ranked based on their overall performance in FPGAs. The characteristic features of each algorithm important from the point of view of its implementation in hardware are identified.

Category / Keywords: benchmarking, hash functions, SHA-3, hardware, FPGA

Publication Info: initial version presented at the Third SHA-3 Candidate Conference

Date: received 29 Jun 2012, last revised 30 Oct 2012

Contact author: kgaj at gmu edu

Available format(s): PDF | BibTeX Citation

Note: Minor revision of Table 7 and Fig. 10.

Version: 20121031:050300 (All versions of this report)

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