Cryptology ePrint Archive: Report 2011/670

SHA-3 on ARM11 processors

Peter Schwabe and Bo-Yin Yang and Shang-Yi Yang

Abstract: This paper presents high-speed assembly implementations of the 256-bit-output versions of all five SHA-3 finalists and of SHA-256 for the ARM11 family of processors. We report new speed records for all of the six implemented functions. For example our implementation of the round-3 version of JH-256 is 35% faster than the fastest implementation of the round-2 version of JH-256 in eBASH. Scaled with the number of rounds this is more than a 45% improvement.We also improve upon previous assembly implementations for 32-bit ARM processors. For example the implementation of Groestl-256 described in this paper is about 20% faster than the arm32 implementation in eBASH.

Category / Keywords: implementation / SHA-3, ARM processors, software implementation

Date: received 9 Dec 2011

Contact author: peter at cryptojedi org

Available format(s): PDF | BibTeX Citation

Version: 20111216:180433 (All versions of this report)

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