Paper 2011/078

A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO

Jean-Luc Beuchat, Eiji Okamoto, and Teppei Yamazaki


We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-$5$ and Virtex-$6$ FPGAs. Our architecture is built around a $8$-bit datapath. The Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and ECHO at all levels of security. Thanks to a careful organization of AES and ECHO internal states in the register file, we manage to generate all read and write addresses by means of a modulo-$16$ counter and a modulo-$256$ counter. A fully autonomous implementation of ECHO and AES on a Virtex-$5$ FPGA requires $193$ slices and a single $36$k memory block, and achieves competitive throughputs. Assuming that the security guarantees of ECHO are at least as good as the ones of the SHA-$3$ finalists BLAKE and Keccak, our results show that ECHO is a better candidate for low-area cryptographic coprocessors. Furthermore, the design strategy described in this work can be applied to combine the AES and the SHA-$3$ finalist {G}røstl.

Available format(s)
Publication info
Published elsewhere. Unknown where it was published
AESECHOhash functionsimplementationSHA-3
Contact author(s)
jeanluc beuchat @ gmail com
2012-09-15: last of 5 revisions
2011-02-20: received
See all versions
Short URL
Creative Commons Attribution


      author = {Jean-Luc Beuchat and Eiji Okamoto and Teppei Yamazaki},
      title = {A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO},
      howpublished = {Cryptology ePrint Archive, Paper 2011/078},
      year = {2011},
      note = {\url{}},
      url = {}
Note: In order to protect the privacy of readers, does not use cookies or embedded third party content.