Paper 2010/536

On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings

Xu Guo, Sinan Huang, Leyla Nazhandali, and Patrick Schaumont


Both FPGAs and ASICs are widely used as the technology for comparing SHA-3 hardware benchmarking process. However, the impact of target technology in SHA-3 hardware benchmark rankings has hardly been considered. A cross-platform comparison between the FPGA and ASIC results of the 14 second round SHA-3 designs demonstrates the gap between two sets of benchmarking results. In this paper we describe a systematic approach to analyze a SHA-3 hardware benchmark process for both FPGAs and ASICs, and we present our latest results for FPGA and ASIC evaluation of the 14 second round SHA-3 candidates.

Note: The paper version 2 contains updated FPGA results with Xilinx Virtex-5 XC5VLX330-2FF1760 FPGA. All the FPGA area, speed and power results are generated based on Xilinx XFLOWcommand-line tool (Version 12.2). All the Verilog/VHDL source codes and FPGA/ASIC scripts for 14 SHA-3 algorithms with the SHA256 reference design can be found at VT-SHA3 project website: (

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Published elsewhere. Unknown where it was published
SHA3 FPGA ASIC benchmark
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xuguo @ vt edu
2010-11-19: last of 3 revisions
2010-10-25: received
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      author = {Xu Guo and Sinan Huang and Leyla Nazhandali and Patrick Schaumont},
      title = {On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings},
      howpublished = {Cryptology ePrint Archive, Paper 2010/536},
      year = {2010},
      note = {\url{}},
      url = {}
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