Hardware Implementation of the SHA-3 Candidate Skein

Stefan Tillich

Paper 2009/159

Hardware Implementation of the SHA-3 Candidate Skein

Stefan Tillich

Abstract

Skein is a submission to the NIST SHA-3 hash function competition which has been optimized towards implementation in modern 64-bit processor architectures. This paper investigates the performance characteristics of a high-speed hardware implementation of Skein with a 0.18\,\textmu}m standard-cell library and on different modern FPGAs. The results allow a first comparison of the hardware performance figures of full Skein with other SHA-3 candidates.

Metadata

Available format(s): PDF
Category: Implementation
Publication info: Published elsewhere. First publication via eprint.
Keywords: SHA-3 Skein high-speed hardware standard-cell library FPGA
Contact author(s): Stefan Tillich @ iaik tugraz at
History: 2009-04-07: received
Short URL: https://ia.cr/2009/159
License: CC BY

BibTeX

@misc{cryptoeprint:2009/159,
      author = {Stefan Tillich},
      title = {Hardware Implementation of the {SHA}-3 Candidate Skein},
      howpublished = {Cryptology {ePrint} Archive, Paper 2009/159},
      year = {2009},
      url = {https://eprint.iacr.org/2009/159}
}