Paper 2008/280

FPGA and ASIC Implementations of the $\eta_T$ Pairing in Characteristic Three

Jean-Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, and Hiroyasu Yamamoto


Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient algorithms and implementations of pairing primitives, the study of hardware accelerators became an active research area. In this paper, we propose two coprocessors for the reduced $\eta_T$ pairing introduced by Barreto {\it et al.} as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We also present the first ASIC implementation of the reduced $\eta_T$ pairing.

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Published elsewhere. Unknown where it was published
Tate pairing$\eta_T$ pairingelliptic curve cryptographyfinite fieldarithmetichardware acceleratorFPGAASIC
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beuchat @ risk tsukuba ac jp
2009-06-17: last of 4 revisions
2008-06-24: received
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      author = {Jean-Luc Beuchat and Hiroshi Doi and Kaoru Fujita and Atsuo Inomata and Piseth Ith and Akira Kanaoka and Masayoshi Katouno and Masahiro Mambo and Eiji Okamoto and Takeshi Okamoto and Takaaki Shiga and Masaaki Shirase and Ryuji Soga and Tsuyoshi Takagi and Ananda Vithanage and Hiroyasu Yamamoto},
      title = {FPGA and ASIC Implementations of the $\eta_T$ Pairing in Characteristic Three},
      howpublished = {Cryptology ePrint Archive, Paper 2008/280},
      year = {2008},
      note = {\url{}},
      url = {}
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