Cryptology ePrint Archive: Report 2008/280

FPGA and ASIC Implementations of the $\eta_T$ Pairing in Characteristic Three

Jean-Luc Beuchat and Hiroshi Doi and Kaoru Fujita and Atsuo Inomata and Piseth Ith and Akira Kanaoka and Masayoshi Katouno and Masahiro Mambo and Eiji Okamoto and Takeshi Okamoto and Takaaki Shiga and Masaaki Shirase and Ryuji Soga and Tsuyoshi Takagi and Ananda Vithanage and Hiroyasu Yamamoto

Abstract: Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient algorithms and implementations of pairing primitives, the study of hardware accelerators became an active research area.

In this paper, we propose two coprocessors for the reduced $\eta_T$ pairing introduced by Barreto {\it et al.} as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We also present the first ASIC implementation of the reduced $\eta_T$ pairing.

Category / Keywords: implementation / Tate pairing, $\eta_T$ pairing, elliptic curve cryptography, finite field, arithmetic, hardware accelerator, FPGA, ASIC

Date: received 20 Jun 2008, last revised 17 Jun 2009

Contact author: beuchat at risk tsukuba ac jp

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Version: 20090617:072622 (All versions of this report)

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