### A Pipelined Karatsuba-Ofman Multiplier over GF($3^{97}$) Amenable for Pairing Computation

Nidia Cortez-Duarte, Francisco Rodríguez-Henríquez, Jean-Luc Beuchat, and Eiji Okamoto

##### Abstract

We present a subquadratic ternary field multiplier based on the combination of several variants of the Karatsuba-Ofman scheme recently published. Since one of the most relevant applications for this kind of multipliers is pairing computation, where several field multiplications need to be computed at once, we decided to design a $k$-stage pipeline structure for $k=1,\ldots,4$, where each stage is composed of a 49-trit polynomial multiplier unit. That architecture can compute an average of $k$ field multiplications every three clock cycles, which implies that our four-stage pipeline design can perform more than one field multiplication per clock cycle. When implemented in a Xilinx Virtex V XC5VLX330 FPGA device, this multiplier can compute one field multiplication over \gf($3^{97}$) in just $11.47$ns.

Available format(s)
Category
Implementation
Publication info
Published elsewhere. Unknown where it was published
Keywords
Finite field arithmeticField Multipliers.
Contact author(s)
francisco @ cs cinvestav mx
History
Short URL
https://ia.cr/2008/127

CC BY

BibTeX

@misc{cryptoeprint:2008/127,
author = {Nidia Cortez-Duarte and Francisco Rodríguez-Henríquez and Jean-Luc Beuchat and Eiji Okamoto},
title = {A Pipelined Karatsuba-Ofman Multiplier over GF($3^{97}$) Amenable for Pairing Computation},
howpublished = {Cryptology ePrint Archive, Paper 2008/127},
year = {2008},
note = {\url{https://eprint.iacr.org/2008/127}},
url = {https://eprint.iacr.org/2008/127}
}

Note: In order to protect the privacy of readers, eprint.iacr.org does not use cookies or embedded third party content.