Paper 2006/403

Non-Wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-bit

Willi Geiselmann and Rainer Steinwandt


Significant progress in the design of special purpose hardware for supporting the Number Field Sieve (NFS) has been made. From a practical cryptanalytic point of view, however, none of the published proposals for coping with the sieving step is satisfying. Even for the best known designs, the technological obstacles faced for the parameters expected for a 1024-bit RSA modulus are significant. Below we present a new hardware design for implementing the sieving step. The suggested chips are of moderate size and the inter-chip communication does not seem unrealistic. According to our preliminary analysis of the 1024-bit case, we expect the new design to be about 2 to 3.5 times slower than TWIRL (a wafer-scale design). Due to the more moderate technological requirements, however, from a practical cryptanalytic point of view the new design seems to be no less attractive than TWIRL.

Available format(s)
Public-key cryptography
Publication info
Published elsewhere. Unknown where it was published
RSAcryptanalytic hardwarefactoring integersNFS
Contact author(s)
rsteinwa @ fau edu
2006-11-12: received
Short URL
Creative Commons Attribution


      author = {Willi Geiselmann and Rainer Steinwandt},
      title = {Non-Wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-bit},
      howpublished = {Cryptology ePrint Archive, Paper 2006/403},
      year = {2006},
      note = {\url{}},
      url = {}
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