Paper 2006/042
Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms
Sourav Mukhopadhyay and Palash Sarkar
Abstract
We consider the problem of efficiently generating sequences in hardware for use in certain cryptographic algorithms. The conventional method of doing this is to use a counter. We show that sequences generated by linear feedback shift registers (LFSRs) can be tailored to suit the appropriate algorithms. For hardware implementation, this reduces both time and chip area. As a result, we are able to suggest improvements to the design of DES Cracker built by the Electronic Frontier Foundation in 1998; provide an efficient strategy for generating start points in time-memory trade/off attacks; and present an improved parallel hardware implementation of a variant of the counter mode of operation of a block cipher.
Note: Earlier work on use of LFSRs for exhaustive key search was kindly pointed out to us by David Wagner. The "Related Works" portion of the current paper discusses this point.
Metadata
- Available format(s)
-
PDF
- Category
- Secret-key cryptography
- Publication info
- Published elsewhere. Unknown where it was published
- Keywords
- DES CrackerTMTOCounter Mode of OperationLFSR
- Contact author(s)
- palash @ isical ac in
- History
- 2006-02-28: revised
- 2006-02-06: received
- See all versions
- Short URL
- https://ia.cr/2006/042
- License
-
CC BY
BibTeX
@misc{cryptoeprint:2006/042,
author = {Sourav Mukhopadhyay and Palash Sarkar},
title = {Application of {LFSRs} for Parallel Sequence Generation in Cryptologic Algorithms},
howpublished = {Cryptology {ePrint} Archive, Paper 2006/042},
year = {2006},
url = {https://eprint.iacr.org/2006/042}
}
